Verification and Synthesis Using Real Quantifier Elimination

Sturm, Thomas; Tiwari, Ashish

doi:10.1145/1993886.1993935

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Verification and Synthesis Using Real Quantifier Elimination

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Sturm, Thomas
Automation of Logic, MPI for Informatics, Max Planck Society;

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Citation

Sturm, T., & Tiwari, A. (2011). Verification and Synthesis Using Real Quantifier Elimination. In A. Leykin (Ed.), ISSAC 2011 (pp. 329-336). New York, NY: ACM. doi:10.1145/1993886.1993935.

Cite as: https://hdl.handle.net/11858/00-001M-0000-0010-14F9-7

Abstract

We present the application of real quantifier elimination to formal verification and synthesis of continuous and switched dynamical systems. Through a series of case studies, we show how first-order formulas over the reals arise when formally analyzing models of complex control systems. Existing off-the-shelf quantifier elimination procedures are not successful in eliminating quantifiers from many of our benchmarks. We therefore automatically combine three established software components: virtual subtitution based quantifier elimination in Reduce/Redlog, cylindrical algebraic decomposition implemented in Qepcad, and the simplifier Slfq implemented on top of Qepcad. We use this combination to successfully analyze various models of systems including adaptive cruise control in automobiles, adaptive flight control system, and the classical inverted pendulum problem studied in control theory.