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Journal Article

Modeling a Hardware Synthesis Methodology in Isabelle

MPS-Authors
http://pubman.mpdl.mpg.de/cone/persons/resource/persons44075

Basin,  David A.
Programming Logics, MPI for Informatics, Max Planck Society;

http://pubman.mpdl.mpg.de/cone/persons/resource/persons44446

Friedrich,  Stefan
Programming Logics, MPI for Informatics, Max Planck Society;

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Citation

Basin, D. A., & Friedrich, S. (1999). Modeling a Hardware Synthesis Methodology in Isabelle. Formal Methods in Systems Design, 15(2), 99-122.


Cite as: http://hdl.handle.net/11858/00-001M-0000-000F-3664-2
Abstract
Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higher-order logic so that circuits are incrementally built during proofs using higher-order resolution. Our interpretation simplifies and extends Formal Synthesis both conceptually and in implementation. It also supports integration of this development style with other proof-based synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parametric designs.