Compaction on the Torus

Mehlhorn, Kurt; Rülling, W.

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Compaction on the Torus

Mehlhorn, K., & Rülling, W. (1990). Compaction on the Torus. IEEE Transactions on CAD of Integrated Circuits and Systems, 9, 389-397.

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-0014-AE5F-0 Version Permalink: https://hdl.handle.net/11858/00-001M-0000-0024-4136-1

Genre: Journal Article

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Creators:
Mehlhorn, Kurt¹, Author
Rülling, W.², Author

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1Algorithms and Complexity, MPI for Informatics, Max Planck Society, ou_24019
2Max Planck Society, ou_persistent13

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Abstract: A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area. An effective compaction system frees the designer from the details of the design rules, and hence, increases his or her productivity and on the other hand produces high quality layouts. A general framework for compaction on a torus is introduced. This problem comes up whenever an array of identical cells has to compacted. The framework is instantiated by several specific compaction algorithms: one-dimensional compaction without and with automatic job insertion and two-dimensional compaction.

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Language(s): eng - English

Dates: Date issued: 1990

Publication Status: Issued

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Rev. Type: Peer

Identifiers: eDoc: 344695
Other: Local-ID: C1256428004B93B8-7575411001D3D220C12571CA00307579-mehlhorn90x

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Title: IEEE Transactions on CAD of Integrated Circuits and Systems

Source Genre: Journal

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Pages: - Volume / Issue: 9 Sequence Number: - Start / End Page: 389 - 397 Identifier: ISSN: 0278-0070