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  Modeling a Hardware Synthesis Methodology in Isabelle

Basin, D. A., & Friedrich, S. (1999). Modeling a Hardware Synthesis Methodology in Isabelle. Formal Methods in Systems Design, 15(2), 99-122.

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-000F-3664-2 Version Permalink: https://hdl.handle.net/11858/00-001M-0000-000F-3668-9
Genre: Journal Article

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 Creators:
Basin, David A.1, Author           
Friedrich, Stefan1, Author           
Affiliations:
1Programming Logics, MPI for Informatics, Max Planck Society, ou_40045              

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 Abstract: Formal Synthesis is a methodology developed at Kent for combining circuit design and verification, where a circuit is constructed from a proof that it meets a given formal specification. We have reinterpreted this methodology in Isabelle's theory of higher-order logic so that circuits are incrementally built during proofs using higher-order resolution. Our interpretation simplifies and extends Formal Synthesis both conceptually and in implementation. It also supports integration of this development style with other proof-based synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parametric designs.

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Language(s): eng - English
 Dates: 2010-03-121999
 Publication Status: Issued
 Pages: -
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 Table of Contents: -
 Rev. Type: Peer
 Identifiers: eDoc: 519766
Other: Local-ID: C1256104005ECAFC-5905BB1B99B7B7E7C12568B200457274-BasinFriedrichVeritas
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Title: Formal Methods in Systems Design
Source Genre: Journal
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Pages: - Volume / Issue: 15 (2) Sequence Number: - Start / End Page: 99 - 122 Identifier: -