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キーワード:
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要旨:
In this survey paper, we compare native double precision solvers with emulated-
and mixed- precision solvers of linear systems of equations as they typically
arise in finite element discretisations. The emulation utilises two single
float numbers to achieve higher precision, while the mixed precision iterative
refinement computes residuals and updates the solution vector in double
precision but solves the residual systems in single precision. Both techniques
have been known since the 1960s, but little attention has been devoted to their
performance aspects. Motivated by changing paradigms in processor technology
and the emergence of highly parallel devices with outstanding single float
performance, we adapt the emulation and mixed precision techniques to coupled
hardware configurations, where the parallel devices serve as scientific
co-processors. The performance advantages are examined with respect to speedups
over a native double precision implementation (time aspect) and reduced area
requirements for a chip (space aspect). The paper begins with an overview of
the theoretical background, algorithmic approaches and suitable hardware
architectures. We then employ several conjugate gradient and multigrid solvers
and study their behaviour for different parameter settings of the iterative
refinement technique. Concrete speedup factors are evaluated on the coupled
hardware configuration of a general-purpose CPU and a graphics processor. The
dual performance aspect of potential area savings is assessed on a field
programmable gate array. In the last part, we test the applicability of the
proposed mixed precision schemes with ill-conditioned matrices. We conclude
that the mixed precision approach works very well with the parallel
co-processors gaining speedup factors of four to five, and area savings of
three to four, while maintaining the same accuracy as a reference solver
executing everything in double precision.
