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キーワード:
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要旨:
Vulnerabilities in computer systems arise in part due to programmer's logical errors,
and in part also due to programmer's false (i.e., over-optimistic) expectations about the
guarantees that are given by the abstractions of a programming language.
For the latter kind of vulnerabilities, architectures with hardware or instructionlevel support for protection mechanisms can be useful. One trend in computer systems protection is hardware-supported enforcement of security guarantees/policies. Capability-based
machines are one instance of hardware-based protection mechanisms. CHERI is a recent implementation of a 64-bit MIPS-based capability architecture with byte-granularity memory protection.
The goal of this thesis is to provide a paper formal model of the CHERI architecture
with the aim of formal reasoning about the security guarantees that can be offered by
the features of CHERI. We first give simplified instruction operational semantics, then we prove that capabilities are unforgeable in our model. Second, we show that existing techniques for enforcing control-flow integrity can be adapted to the CHERI ISA. Third, we show that one notion of memory compartmentalization can be achieved with the help of CHERI's memory protection. We conclude by suggesting other security building blocks that would be helpful to reason about, and laying down a plan for potentially using this work for building a secure compiler, i.e., a compiler that preserves security properties.
The outlook and motivation for this work is to highlight the potential of using CHERI
as a target architecture for secure compilation.
