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  Generating Code from Abstract VHDL Models

Abdel Maksoud, M. (2007). Generating Code from Abstract VHDL Models. Master Thesis, Universität des Saarlandes, Saarbrücken.

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-0027-D127-5 Version Permalink: https://hdl.handle.net/21.11116/0000-0001-9BEB-8
Genre: Thesis
Latex : Generating Code from Abstract {VHDL} Models

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Masterarbeit-Mohamed-Maksoud-2007.pdf (Any fulltext), 706KB
 
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 Creators:
Abdel Maksoud, Mohamed1, Author           
Wilhelm, Reinhard2, Advisor
Affiliations:
1International Max Planck Research School, MPI for Informatics, Max Planck Society, Campus E1 4, 66123 Saarbrücken, DE, ou_1116551              
2External Organizations, ou_persistent22              

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Language(s): eng - English
 Dates: 20072007
 Publication Status: Issued
 Pages: -
 Publishing info: Saarbrücken : Universität des Saarlandes
 Table of Contents: -
 Rev. Type: -
 Identifiers: BibTex Citekey: Maksoud2007
 Degree: Master

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