非表示:
キーワード:
-
要旨:
Logic programs can be synthesized as a by-product of the planning of
their verification proofs. This is achieved by using higher-order
variables at the proof planning level, which become instantiated in
the course of planning. We illustrate two uses of such variables in
proof planning for program synthesis, one for synthesis proper and one
for the selection of induction schemes. We demonstrate that the use of
these variables can be restricted naturally in such a way that terms
containing them form a tractable extension of first-order terms.
